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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:26:52 04/12/2012 
-- Design Name: 
-- Module Name:    ShitfRegister_SIPO_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.FAW_TYPES.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ShiftRegister_SIPO_test is
    Port ( data_in : in  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           en : in  STD_LOGIC_VECTOR (SR_CELLS-1 downto 0);
           sset : in  STD_LOGIC;
           sclear : in  STD_LOGIC;
           data_out : out  SR_DATA_OUT_BUS;
			  internal_bus: inout SR_DATA_OUT_BUS
			  );
end ShiftRegister_SIPO_test;

architecture Behavioral of ShiftRegister_SIPO_test is

	component SR_CELL is
		port(
			d : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			clk : IN STD_LOGIC;
			sclr : IN STD_LOGIC;
			sset : IN STD_LOGIC;
			q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
	end component;

--signal internal_bus : SR_DATA_OUT_BUS;

begin

	ShiftRegisterFirstCell : SR_CELL
		port map(
			clk=>clk,
			d=>data_in,
			q=>internal_bus(0),
			sclr=>sclear,
			sset=>sset
		);
	
	ShiftRegisterInternal : for i in 1 to SR_CELLS-1 generate
		comp: SR_CELL
		port map(
			clk=>clk,
			d=>internal_bus(i-1),
			q=>internal_bus(i),
			sclr=>sclear,
			sset=>sset
		);
	end generate ShiftRegisterInternal;
	
	processo:process(clk)
		
		begin
			if (clk'event and clk='1') then
				for i in 0 to SR_CELLS-1 loop
					if(en(i)='1')then
						data_out(i)<=internal_bus(i);
					else
						data_out(i)<= (others=>'Z');
					end if;
				end loop;
			end if;
		end process;
		
end Behavioral;

